Analog Mixed Signal Circuit Design

Job Responsibility:

Analog / SERDES Circuit Design

·Architect, design, and simulate analog circuit blocks that comprise the AFE, including:

oTransmit (TX) circuits: line drivers, pre‑drivers, output stages

oReceive (RX) circuits: front‑end amplifiers, CTLE, PGA, slicers

oClocking circuits: PLLs, DLLs, clock distribution, jitter filtering

·Translate system‑ and PHY‑level requirements into robust block‑level specifications.

·Optimize designs for linearity, noise, jitter, power, area, and robustness.

·Perform detailed transistor‑level simulations across PVT corners and full automotive temperature ranges.

Silicon Bring‑Up, Debug & Production Support

·Support silicon bring‑up, characterization, and validation of analog/SERDES blocks.

·Correlate simulation results with silicon measurements and drive design improvements.

·Collaborate with layout, digital, DSP, systems, test, and product engineering teams.

·Drive resolution of performance, yield, and reliability issues through root‑cause analysis.

Technical Leadership (Principal / Sr Principal Scope)

·Serve as block‑level technical owner for critical analog/SERDES functions.

·Participate in and lead technical design reviews.

·Influence AFE and PHY architecture decisions through deep technical expertise.

·Mentor senior and mid‑level designers and contribute to design best practices.

Job Qualification:

Education

·MSEE or PhD in Electrical Engineering or equivalent (strongly preferred).

Experience

·12–15+ years of experience in analog or mixed‑signal IC design (Principal).

·15–20+ years of experience for Senior Principal level.

·Proven hands‑on experience designing high‑speed SERDES or wireline analog circuits.

·Demonstrated success delivering TX, RX, and clocking circuits to production silicon.

·Extensive experience with circuit design, simulation, and debug at the transistor level.

Examples of Core Technical Expertise

·High‑speed TX and RX circuit design

·Linearity, distortion, and noise analysis

·Jitter generation, tolerance, and clock integrity

·PLL / DLL and clocking architectures

·PVT variation and automotive robustness

·Advanced CMOS processes for high‑speed analog

Highly Desired Experience

·Direct experience with one or more of the following:

10GBASE‑T

10GBASE‑T1 (Automotive Ethernet)

TDD‑based transceivers

Familiarity with automotive semiconductor requirements (AEC‑Q100, temperature, EMI/EMC).

Experience supporting automotive production ramp and customer qualification.

Exposure to ISO 26262 / functional safety concepts is a plus.

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.
Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:

$191,500 to $263,300 annually

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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