Ciena

ASIC Synthesis and STA Engineer - New Grad

Canada · Work style not stated · Full time

Apply on the employer’s site ↗See how well you match this job

You apply directly with the employer. ROLIVA does not submit applications from this page and is not the employer.

About the role

Description from the employer’s posting. Check the employer’s page for the current version.

  • EmployerCiena
  • LocationCanada
  • Work styleWork style not stated
  • Employment typeFull time
  • Employer posted

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. This role offers the opportunity to shape the front-end implementation of industry leading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of high-performance optical networking.

How you will make an impact:

Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation

Show full description

Develop and maintain timing constraints to support synthesis and signoff for subsystem integration

Perform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout preand postlayout stages

Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity

Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows

Implement engineering change orders (ECOs) to support iterative design refinement

Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities

The must haves:

B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)

Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation

Familiarity with RTL design principles and hardware description languages

Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules

Nice to haves:

Experience with additional frontend or backend design activities such asfloorplanning, Design for Testability (DFT), or place and route

Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment

Handson exposure to deepsubmicron ASIC technologies and advanced timing closure methodologies

Scripting experience (e.g., Python,Tcl, or similar) to enhance automation and debug workflows

Background supporting DSPcentric or highspeed ASIC development programs

Experience working with external EDA vendors or foundry technology teams

Pay Range:

The annual salary range for this position is $70,700 - $112,900

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Staying safe while you apply

  • Never pay to apply, interview or accept an offer. ROLIVA never asks you for payment to apply to a job.
  • Apply only through the official “Apply on the employer’s site” button, on the employer’s own site, and check that a recruiter’s email uses that employer’s own domain rather than a free email address.
  • Be cautious of an offer made with no real interview, or pressure to decide quickly or share financial details early.

Does something look wrong with this listing? Use “Report broken link” in the role details, or read ROLIVA’s full job-safety guidance ↗.

Preparing for this role with ROLIVA

  • Check the fit.

    Compare the requirements with the experience you have confirmed, including gaps.

  • Prepare honestly.

    Build interview stories and application drafts from your own evidence.

  • Keep track.

    Save the role and record your own application status and follow-ups.

Create a free workspace or log in.

At a glance

  • Employment typeFull time
  • Employer posted
  • Added to ROLIVA
  • Last checked

Skills in this posting

Skills ROLIVA found in the employer’s own description above. A mention is not a requirement.

Python

Explore similar roles

Similar jobs