Associate Staff/Staff Implementation Design Engineer

Experience Level: 9-10 years

Education Requirements: Bachelor’s/Master’s degree in ECE, EEE or related fields.

Key Responsibilities:

Hands-on development, management and validation of timing constraints for RTL-to-GDSII flow in collaboration with Design & DFT teams

Own STA execution for digital blocks and top-level designs

Help in CTS spec generation in collaboration with Design & PnR engineers.

Run Logical Equivalence checks using industry standard tools

Develop low power and UPF development & lowe power checks

Generate and interpret timing reports using industry-standard tools

Implement timing ECOs to resolve critical path issues

Contribute to timing methodology improvements and automation

Perform timing checks for CDC, false paths, and multicycle paths

Lead the team and execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).

Own and optimize power, performance, and area (PPA) metrics for assigned

designs.

Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR

drop, EM, DRC/LVS).

Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure

seamless integration.

Drive EDA tool flow automation and methodology enhancements for improved

efficiency and scalability.

Mentor and guide junior engineers, fostering technical growth and design

excellence.

Must Have Requirements

Bachelor’s or Master’s degree in ECE, EEE, VLSI or related field.

9-10 years of experience in ASIC physical design

Hands-on expertise in Industry standard EDA tools: Cadence (Genus, Innovus, Tempus, LEC, CLP), or equivalent or Synopsys (ICC2, Fusion Compiler, PrimeTime)

Strong background in synthesis, constraints, margins and timing analysis/fixing.

Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS).

Solid understanding of architecture-to-GDSII flows and sign-off requirements.

Excellent problem-solving and communication skills.

Preferred Qualifications

Experience with chip-level integration and hierarchical design methodologies.

Familiarity with DFT, Floor planning, PnR, and physical verification/IR analysis.

Exposure to multi-clock, multi-voltage, and multi-domain designs

Experience of leading small (4-10 members) teams in related domain.

Automation expertise using perl/tcl/tk/python.

Exposure to multi site environment and collaboration.

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

Medical and dental insurance coverage including spouse and child(ren)

Bi yearly health screening and flu vaccination

Office location is above Tai Seng MRT station

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Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.