Datacenter & Agentic AI Workload Performance Optimization Engineer

This role isremote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You’re a performance engineer who enjoys getting deep into runtimes, compilers, applications, and CPU microarchitecture to understand why software is fast—or slow.
• You have hands-on experience optimizing software on RISC-V or another modern CPU architecture, with a strong understanding of the hardware/software boundary.
• You’re comfortable profiling complex systems, finding bottlenecks, forming hypotheses, and iterating through optimizations using data.
• You’re excited about emerging agentic AI development workflows and using AI tools to automate profiling, coding, benchmarking, and optimization.
• You’re a strong technical collaborator who can work across compiler, runtime, systems software, hardware, and performance modeling teams.

What We Need

• Master’s or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field, with strong experience in performance optimization, computer architecture, compilers, or systems software.
• Hands-on experience with runtime or compiler optimization, such as OpenJDK/JIT, LLVM, GCC, V8, Python, or equivalent systems.
• Strong understanding of CPU performance, memory hierarchies, concurrency, garbage collection, vector/SIMD optimization, and RISC-V architecture.
• Expertise with performance profiling and analysis tools such as Linux perf, runtime profilers, QEMU, tracing tools, and performance modeling environments.
• Strong programming skills in Java, Python, C/C++, and RISC-V assembly, with the ability to work effectively across multiple software layers.

What You Will Learn

• How to optimize modern software stacks from application and runtime all the way down to CPU microarchitecture and silicon.
• How RISC-V Vector, Matrix, and custom ISA capabilities can be used to accelerate real-world datacenter and AI workloads.
• How runtime, compiler, memory, and concurrency decisions impact performance at datacenter scale.
• How to build automated and AI-assisted performance optimization workflows that continuously profile, analyze, modify, and benchmark software.
• How to influence future CPU architecture by connecting real workload behavior and software optimization opportunities to hardware design decisions.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.