Design Engineering Architect

Job Overview:

The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume.

The Cadence IP Vision is to deliver industry leading IP solutions to enable our customers to be successful across these fast-moving application spaces.

The Design Engineering Architect will be based in Cork, as part of an experienced Controller IP Team with long established IP development sites in Europe, US and India.

Job Responsibilities:

• Technical leadership of complex IP such as UCIe, Ethernet, HBM, and PCIe.
• Collaborate with system architects and product managers to define the architecture and specifications on standards such as UCIe, considering factors such as data rate, power consumption, and compatibility with industry standards.
• Hands-on leadership of RTL development from micro-architecture definition to IP sign-off for general release..

• Contribute to planning of activities and milestones for the digital development teams.
• Leadership of cross-functional technical meetings with Analog & Software counterparts.
• Support customer pre-sales and post-sales meetings.
• Develop, maintain and improve upon processes and procedures for efficient product execution, IP quality and industry best practices.
• Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
• Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI-SIG, JEDEC, UCIe
• Represent Cadence by presenting at Industry Conference such as IEEE, DAC.

Job Qualifications:

• Degree in Electrical/Electronic Engineering, microelectronics, or a related discipline.
• 15-20 years’ experience in microelectronics industry.
• Expert in Verilog/System Verilog RTL design essential.
• Expert in front-end design tools covering LINT, synthesis, CDC/RDC analysis essential.
• Experience of SoC architecture and development essential.
• Experience of technical team leadership essential.
• Excellent oral and written English essential.
• Self-motivated with excellent planning, interpersonal and with the ability to communicate complex concepts clearly and thoroughly.

Additional Skills/Preferences:

• Experience of Metric Driven Verification (MDV) and UVM desired.
• Experience of industry standard protocols such as AXI, CHI-C2C & CXS.B preferred.
• Experience of quality processes, such as ISO-9001 & ISO-26262 preferred.

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel: <10%

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