FPGA Compiler (Placer) Engineer

Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality.

The ideal candidate brings strong expertise in EDA algorithms, large-scale system optimization, and FPGA/ASIC physical design flows, along with a passion for solving complex, performance-critical problems.

Key Responsibilities:

Placement Algorithm Development:
Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.

Compiler Flow Enhancement:
Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.

Performance Optimization:
Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.

Timing-Driven Placement:
Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.

Cross-Functional Collaboration:
Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.

Debug & Analysis:
Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.

Toolchain Integration:
Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Why Join Altera?

Work on core compiler technology that directly impacts FPGA performance and usability

Solve challenging algorithmic problems at scale

Collaborate with world-class teams across architecture, silicon, and software

Salary

The pay range below is for Bay Area California only. Actual salary may vary based ona number offactors including job location, job-related knowledge, skills, experiences,trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149.1K- $215.9KUSD

We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.

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Qualifications:

Minimum Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.

Experiencein algorithms and data structures (optimization, graph theory, heuristics)

Experience with placement algorithms or physical design flows

Experience in C/C++ and software engineering best practices

Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering)

Experience with Timing-driven and congestion-driven optimization

Experience in ASIC or FPGA physical design methodologies

Experience in solving complex, large-scale optimization problems with high performance and scalability requirements.

Preferred Qualifications

Experience with FPGA toolchains (e.g., Quartus, Vivado)

Knowledge of FPGA architectures and interconnect fabrics

Familiarity with routing and timing closure techniques

Experience with parallel or distributed algorithms for EDA tools

Scripting experience (e.g., Python, Tcl) for tooling and automation

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.