FPGA Design Engineer

Responsibilities:

• RTL Development & Verification: Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
• FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
• System-Level Integration: Collaborate directly with hardware and software engineering teams to drive rapid bring-up and debugging of next-generation network switch platforms.
• Design & Architecture Reviews: Actively participate in peer RTL code reviews, as well as PCB schematic and board design reviews.
• Toolchain Automation: Develop AI-skills, Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows

Concepts & Skills You Will Gain

• Switching Architectures: Master data and control path architectures in modern Ethernet switches, alongside critical I/O interfaces (e.g., PCIe, Interlaken, Ethernet PHY/MAC, SMBus, SPI, MDIO, JTAG).
• Networking Protocols: Gain hands-on experience with Ethernet-based protocols, including PTP, sFlow, and PoE.
• Practical FPGA Engineering: Learn to navigate real-world design challenges, including tight timing closure, resource optimization, clock domain crossing, and complex state machine design.
• Multi-Vendor Ecosystems: Develop expertise across major vendor FPGA architectures, toolchains, and IDEs.
• Cross-Functional System Design: Build skills in interpreting complex PCB schematics, running advanced simulation frameworks, and solving multidisciplinary hardware/software challenges.

• 5 years or more of hands-on experience in Verilog/SystemVerilog RTL design.
• Proven background in Control Path design.
• Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI).
• Local to the area

Preferred:

• Experience with Ethernet Data Path architecture and design.
• Hands-on experience with Streaming Bus interfaces (e.g., AXI-Stream).
• Background in FPGA resource management and timing closure.
• Proficiency in Python, Tcl, or general scripting for EDA tool automation.
• Lab Debugging & Validation: Utilize logic analyzers (LA), oscilloscopes, and vendor-specific debug tools for lab bring up, debug, and validation.

Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.