Altera

FPGA Development Tools Engineer

United Kingdom · Work style not stated · Full time

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About the role

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EmployerAltera
LocationUnited Kingdom
Work styleWork style not stated
Employment typeFull time
Employer posted10 Jun 2026

Job Details:

Job Description:

Altera develops world-class Field Programmable Gate Array (FPGA) technology which comprises both the FPGA hardware itself and the associated software components, including tools for High-Level Design (HLD) entry.

The two major Altera HLD tools are DSP Builder (based on MATLAB/Simulink) and HLS which are built on a common HLD compiler stack. The HLD compiler generates highly-optimised FPGA RTL including automatic device mapping and pipelining. DSP Builder and HLS users can therefore focus on the architecture of their design without needing to spend time writing and re-writing RTL.

Altera is looking for engineers to join our teams. As a member of the UK DSP Builder team within the HLD group, you will be responsible for:

developing and supporting DSP Builder

designing and implementing improvements in the HLD compiler stack.

Show full description

Your work will include:

analysis of bottlenecks in user designs and the corresponding implementation of compiler optimizations

comprehensive benchmarking of the FPGA-targeted generated hardware. As optimization is a global problem, the work may involve a mix of compiler software development and digital hardware design.

UK Altera office is in Marlow, 40 minutes from central London and Oxford.

Qualifications:

Masters Degree or five years commercial experience in Computer Science, Software Engineering, Computer Engineering, Electrical Engineering or related fields

Strong software skills using C/C++, including working knowledge of efficient data structures and algorithms

Technical knowledge and appreciation of digital hardware design concepts

Good problem solving skills

Good interpersonal and communication skills

Preferred Qualifications

Experience with digital hardware design using Verilog/VHDL and related design flows

Experience in developing optimizing compilers

Experience with FPGAs

Job Type:

Regular

Shift:

Shift 1 (United Kingdom)

Primary Location:

Marlow, Buckinghamshire, United Kingdom

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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