NXP
G7 Fellow – High-Speed Interfaces & Clocking Strategy
India · Work style not stated · Full time
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About the role
Description from the employer’s posting. Check the employer’s page for the current version.
- EmployerNXP
- LocationIndia
- Work styleWork style not stated
- Employment typeFull time
- Employer posted
Key Responsibilities
Technology Strategy & Roadmap Leadership
- Define and drive NXP’s long-term strategy for high-speed interfaces, clocking architectures, PLL technologies, and associated analog foundation IP.
- Analyze current and future requirements across all NXP Business Lines and Product Lines.
- Develop technology roadmaps aligned with market trends, customer needs, and product strategies.
- Identify opportunities for technology consolidation, platform reuse, and architectural alignment across NXP.
- Establish strategic priorities and investment recommendations to strengthen NXP’s competitive position.
Portfolio Analysis & Make-or-Buy Decisions
- Assess NXP’s portfolio requirements across automotive, industrial, secure connected edge, networking, and computing applications.
- Evaluate internal capabilities, external IP offerings, partnerships, and acquisition opportunities.
- Develop and recommend make-versus-buy strategies for PHYs, SerDes, clocking, PLL, and related technologies.
- Provide strategic guidance on technology investments based on technical differentiation, reuse potential, time-to-market, and business impact.
Show full description
Clocking & PLL Technology Leadership
- Define company-wide clocking and synchronization strategies.
- Drive the roadmap for next-generation clock generation and PLL solutions with focus on:
- Low jitter
- Low power
- Small area
- Scalability across process nodes
- High-performance operation
- Functional safety requirements
- Lead development of architectural frameworks for clock distribution, synchronization, timing integrity, and system-level clock management.
High-Speed Interface Architecture
- Provide technical leadership for connectivity technologies including:
- I3C
- USB / eUSB
- Ethernet
- USXGMII
- MIPI
- DDR
- PCIe
- CXL
- UCIe
- Emerging chiplet interconnect technologies
- Guide future PHY and SerDes architectures supporting multi-gigabit and chiplet-based systems.
Innovation & Technical Excellence
- Establish and maintain a long-term innovation roadmap for high-speed interfaces and clocking technologies.
- Anticipate emerging industry trends and identify opportunities for NXP differentiation.
- Drive benchmarking, technology assessments, and architectural studies.
- Foster technical excellence and innovation across engineering communities.
- Represent NXP in strategic technical discussions with customers, partners, standards bodies, and ecosystem leaders.
More information about NXP in India...
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At a glance
- Employment typeFull time
- Employer posted
- Added to ROLIVA
- Last checked