Arista Networks

Hardware Design Integrity Engineer

Santa Clara, CA, United States · On-site · Full-time

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About the role

Description from the employer’s posting. Check the employer’s page for the current version.

EmployerArista Networks
LocationSanta Clara, CA, United States
Work styleOn-site
Employment typeFull-time
Employer posted1 month ago

Who You’ll Work With

Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state-of-the-art products that drive network performance and reliability.

What You'll Do

Our Hardware Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscaler datacenters and bleeding edge AI clusters. With this comes complex, oftentimes cross-platform issues requiring engineers passionate about debugging and delivering root cause analysis and fixes to the design team, executives, and customers.

Candidates for this position would be responsible for debugging production system problems and delivering solutions.

Deep dive into various aspects of any existing hardware design - CPU/ASIC, power, SI, clocking, PCIE, optics, fab, components.
Work closely with sw & customer teams on high pressure escalations from the field, including reading logs, identifying the bug, determining the best fix with minimal interruption to the field, delivering the final solution, determining if any other systems are susceptible, and implementing measures to prevent the issue from occurring again.
Writing scripts to look for specific information in the logs or to capture information in live debug sessions
Work closely with the hw design team, but also be able to make firmware, schematic, BOM, fab changes as needed.
Lab measurements and debug.
Work closely with component, FA, ODM teams to identify component level or third party RCAs and fixes needed.
Identify test escapes. Work with the design validation team to examine current test limitations and develop new tests.
Write and present root cause analysis for executives and customers.

Show full description

BSEE or MSEE
5+ years of relevant experience in hardware engineering
Experience debugging Networking Hardware
Experience with proper design of 20+ layer count boards featuring 50G+ signals
Experience debugging and validating multi-phase DC/DC’s for high current, high transient loads
Experience with design and debug of high speed interfaces (DDR, PCIe) as well as low speed signals (I2C, SPI)
Familiarity with signal integrity and power integrity concepts and tools, such as: impedance, PDN’s, Bode plots, PCIE analyzers, TDR’s, VNA’s
FPGA design using Verilog

Compensation Information:

The new hire base pay for this role has a salary range of $130,000 to $225,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

#LI-AC1

Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.

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