Samsung
HW I/P Lab Lead
India · On-site
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About the role
Description from the employer’s posting. Check the employer’s page for the current version.
- EmployerSamsung
- LocationIndia
- Work styleOn-site
- Employer posted
Position Summary
Group Leader for HW IP Group
Role and Responsibilities
As the leader of Hardware IP Design, development and validation, you will head engineering team responsible for the architecture, design and verification of our next generation purpose specific custom HW IP. This critical leadership role spans both in-house IP development as well as strategic evaluation, integration and validation of various other IP blocks. You will bridge the gap between technical execution and people leadership, ensuring delivery, high quality, high performance and power – efficient hardware Ips that drive and differentiate our product line over competitors
Skills and Qualifications
LEADERSHIP AND PEOPLE MANAGEMENT:
- Manage and Mentor a multi-disciplinary team of RTL Design and Design Verification Engineers
- Foster a culture of technical excellence, continuous learning and meaningful collaboration
- Drive Skill up, career development and performance enhancement of the team, in a continuous fashion
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TECHNICAL EXECUTION AND DELIVERY:
- Oversee the end-to-end IP lifecycle. Including micro architecture definition, RTL Coding and Advanced verification
- Ensure robust validation methods utilised to ensure zero-bug silicon
- Define and Implement best-in-class engineering practices, checklists and design flows to maximise efficiency
TECHNICAL COMPETENCIES:
- RTL Design / Verification / Emulation
- Understanding of digital design principles, algorithm, design and Architecture specifications
- Understanding of SystemC , C and Python Programming
- Design direction in terms of performance, gate count and power for various digital designs
- Proficient in System Verilog/UVM/OVM
- FPGA IP/Custom ASIC Prototyping and Validation
- Developing scalable Test benches in System Verilog and UVM
- Understanding of cameras / multimedia / display /NPU subsystems in detail
- Proven track record of integrating complex sub-systems (PCIe, USB, DDR, ARM/RISC-V Cores, MIPI etc)
- Design - knowledge in Verilog, Linting, (CDC) clock domain crossing, synthesis, Timing Analysis, Low Power Implementation (UPF/CPF, Clock Gating, Power Domain)
- Usage for AI Tool e.g., Claude for IP development enhancement, KPI exploration.
KEY LEADERSHIP TRAIT:
- People Developer
- Cross Functional Bridge
- Resource Optimiser
- Decisive Problem Solver
- Influencer and Navigator
DESIRED QUALIFICATION
- Graduate / Postgraduate in Electrical / Electronic Engineering / VLSI Design / Microelectronics
** Samsung/SRI-B has a strict policy on trade secrets. In applying to Samsung/SRI-B and progressing through the recruitment process, you must not/ you are not required to disclose any trade secrets of your current or previous employer.
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At a glance
- Work styleOn-site
- SeniorityLead / Principal
- Employer posted
- Added to ROLIVA
- Last checked
Skills in this posting
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