IP RTL Design Engineer

Role and Responsibilities

Samsung Semiconductor India Research (SSIR) is seeking an experienced RTL/Logic Design Engineer to join the Memory PHY IP development team. The role will focus on the development of HBM, LPDDR PHY projects, delivering high‑performance PHY IP for our customers and providing post‑silicon support.

Write, verify, and maintain synthesizable RTL for LPDDR PHY blocks

- Write SDC constraints, synthesize and ensure timing closure.

- Setup and run IPXACT, LINT, CDC, SDC, PreSTA, DFT and ATPG checks

- Support silicon validation bring-up and debug post-silicon issues

- Work closely with internal and external customers to understand requirements and timely deliverables

Required Qualifications:

- 4 years of full‑cycle RTL/logic design experience, preferably in memory‑PHY or high‑speed interface IP.

- Strong RTL coding background (Verilog/SystemVerilog)

- Proficiency with QC tools such as LINT, CDC, DFT, ATPG

- Experience in SDC creation, Synthesis & STA

- Prior work on LPDDR, HBM PHY projects is preferred

Skills and Qualifications

Experience – 4 to 10 Years of experience

Qualifications

B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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