Lead Design Engineer

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Responsibility

Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.

• Work on RTL synthesis and floorplanning
• Build clock trees and perform optimizations
• Close timing, IR drop and physical verification
• Review and Document designs for taping out
• Interface with Front End RTL design teams and Back End Verification teams

Position Requirements/Qualifications:

• BS degree in Electrical Engineering with a minimum of 5 years of experience OR MS with a minimum of 3 years of experience
• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
• Experience with advanced technologies like 5nm, 3ns and 2nm nodes
• Experience using Linux servers, Script development using Shell/Perl/TCL/Python
• Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

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