Cadence

Lead Design Engineer(Virtual Solution)

China · Work style not stated · Full time

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About the role

Description from the employer’s posting. Check the employer’s page for the current version.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
Develop end-to-end verification flows including:

Optimize solutions for performance, scalability, and emulation efficiency
Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
Support customer enablement, including bring-up, debug, and solution deployment

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Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience
Strong expertise in high-speed protocols such as:

RTL design experience (SystemVerilog / Verilog)
C/C++ development experience for modeling, testbench, or system integration
Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred
Good debugging skills for complex system integration issues

Preferred Qualifications

Experience developing or using AVIP (Accelerated VIP) solutions
Experience with end-to-end system validation flows (simulation → emulation → prototyping)
Knowledge of UVM and verification frameworks
Knowledge of Qemu/Gem5 or other system emulation projects
Experience with multi-language environments (SV + C/C++ + Python)
Familiarity with Emulation/Prototyping flows
Exposure to AI/ML techniques applied to verification or tooling
Strong problem-solving skills and ability to work independently

Soft Skills

We’re doing work that matters. Help us solve what others can’t.

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