Lead DFT Engineer

Key Responsibilities:

Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.

Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.

Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.

Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.

Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements:

Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Bachelor’s degree in a related field.

Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus).

Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687)and boundary scan (IEEE 1149.1/6).

Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).

Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.

EnCharge AI is an equal employment opportunity employer in the United States.

The salary range for this position is $200,000 to $250,000 USD/CAN per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience.