GlobalFoundries
Lead DFT Engineer - MBIST
India · Work style not stated · Full time
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About the role
Description from the employer’s posting. Check the employer’s page for the current version.
- EmployerGlobalFoundries
- LocationIndia
- Work styleWork style not stated
- Employment typeFull time
- Employer posted
About GlobalFoundries
GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Role Summary:
We are seeking an experienced Design-for-Test (DFT) Engineer at the Senior Member of Technical Staff (SMTS) level with over 10 years of industry experience. The candidate will be responsible for architecting, implementing, and validating advanced DFT solutions across complex SoCs. The role requires strong expertise in MBIST, SCAN Insertion, ATPG and simulation (RTL & GLS), and close collaboration with PnR teams to ensure testability and design closure.
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Key Responsibilities
- Define and implement DFT architecture including Scan, MBIST, and Test Access Mechanisms.
- Lead Scan Insertion, ATPG Pattern Generation
- Develop and integrate MBIST solutions for embedded memories (SRAM/MRAM/ROM).
- Perform RTL-level DFT verification and debug.
- Execute and debug Gate-Level Simulations (GLS) with SDF back-annotation.
- Validate Scan Patterns, MBIST controllers, and test protocols across multiple modes (functional/scan/mbist test).
- Redundancy analysis (RA) flows
- Fuse/OTP programming for repair implementation
- Integration of repair signatures into test and bring-up flows
- Drive ATPG pattern generation, validation, and coverage improvement.
- Analyze failure logs and debug issues during simulation and silicon bring-up.
- Collaborate closely with Physical Design (PnR) teams for:
- Scan chain stitching and reordering.
- Write SDC for timing closure for test paths.
- Understand physical impacts of DFT (congestion, timing, power).
- Support silicon bring-up, ATE debugging, and manufacturing test strategies.
Required Qualifications:
- BSEE/MSEE in Electrical Engineering with 10+ years of strong hands‑on experience in JTAG, Scan, Memory BIST, and ATPG
- Proficient in SystemVerilog and UVM‑based verification environments.
- Expertise with ATPG and MBIST tools, particularly Tessent (mandatory).
- Strong proficiency in testbench development, simulation, and debug.
- Experience in post‑silicon failure analysis, diagnostics, and debug.
- Ability to work with ATE patterns and perform gate‑level simulations.
- Skilled in scripting and automation using Tcl, Python, and Shell.
- Experience in RTL development and functional verification of logic circuits is an added advantage.
Preferred Qualifications:
- Experience in RTL development and functional verification of logic circuits.
- Strong communication skills and ability to work in cross-functional teams.
GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.
As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.
All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.
Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia
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At a glance
- Employment typeFull time
- SeniorityLead / Principal
- Employer posted
- Added to ROLIVA
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Skills in this posting
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