Lead Hardware Engineer - DFT IP R&D

Job Responsibilities:

You will play a key role in developing cutting-edge design-for-testability (DFT) tools, contributing to improved usability and quality through feature enhancement and rigorous verification. The role’s day to day responsibilities cover:

Designing and verifying Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features, including new DFT IPs, full scan, compressed/uncompressed scan, memory BIST, JTAG, IEEE 1500, and boundary scan at block and SoC levels.
Providing R&D support to application and product engineers, including problem analysis, debugging, and the development of new features to optimize synthesis results for timing, area, and power.

There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out!

Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their problem-solving skills into professional engineering skills.

Job Qualifications:

• Proficient in RTL design using Verilog and SystemVerilog.
• In-depth knowledge of front-end EDA tools (Verilog/SV simulators, linters, CDC checkers).
• Experience with SystemVerilog assertions, checkers, and advanced verification techniques.
• Knowledge of scripting languages, particularly Perl or Python is highly desirable.
• Knowledge of DFT methodologies is a plus.
• Strong foundational knowledge of data structures and algorithms.
• Familiarity with synthesis, static timing analysis (STA).
• Excellent written and verbal communication and presentation skills.
• Experience and understanding of EDA tool development concepts is a plus.

Position Qualifications:

• M.Tech, M.E, B.Tech, B.E. in EE/ECE/CS or Equivalent
• Good understanding of Digital Electronics.
• Prior knowledge of Verilog/System Verilog and EDA tools required.

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