Astera Labs

Lead Logic Design Engineer

Bengaluru, Karnataka, India · Work style not stated

Apply on the employer’s site ↗See how well you match this job

You apply directly with the employer. ROLIVA does not submit applications from this page and is not the employer.

About the role

Description from the employer’s posting. Check the employer’s page for the current version.

EmployerAstera Labs
LocationBengaluru, Karnataka, India
Work styleWork style not stated
Employer posted1 month ago

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Lead Logic Design Engineer – UALink IP/Subsystem

Experience

6–10 years

Job Summary

Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.

Show full description

Key Responsibilities

Lead UALink IP/subsystem RTL development.

Translate protocol requirements into detailed microarchitecture.

Design high-performance control and data-path logic.

Work on buffering, arbitration, flow control, ordering, and error handling.

Develop and review SystemVerilog RTL.

Drive performance, area, power, and latency optimization.

Collaborate with verification, SoC integration, and physical design teams.

Debug complex functional and integration issues.

Review RTL and mentor engineers.

Support silicon debug and issue resolution.

Required Skills

Strong RTL and microarchitecture experience.

Experience with high-speed interconnects.

Strong understanding of data movement, flow control, arbitration, and buffering.

Excellent SystemVerilog/Verilog skills.

Experience with CDC, lint, synthesis, and timing.

Strong debugging and technical leadership skills.

Preferred

Direct UALink experience.

Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.

Experience with AI/accelerator or high-performance compute SoCs.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

See how well you match this job Apply on the employer’s site ↗

Check your resume against this job Free, no sign-up. Nothing you paste is stored.

Staying safe while you apply

Never pay to apply, interview or accept an offer. ROLIVA never asks you for payment to apply to a job.
Apply only through the official “Apply on the employer’s site” button, on the employer’s own site, and check that a recruiter’s email uses that employer’s own domain rather than a free email address.
Be cautious of an offer made with no real interview, or pressure to decide quickly or share financial details early.

Does something look wrong with this listing? Use “Report broken link” in the role details, or read ROLIVA’s full job-safety guidance ↗.

Preparing for this role with ROLIVA

Check the fit.
Compare the requirements with the experience you have confirmed, including gaps.
Prepare honestly.
Build interview stories and application drafts from your own evidence.
Keep track.
Save the role and record your own application status and follow-ups.

Create a free workspace or log in.