Lead Product Engineer - Design Verification (MM/VIP)

Job Summary

Drives development of products and technologies and has material responsibility for the success of that product/technology. MM VIP PE is expected to become an expert in the Memory domain of Verification IP family – protocol and product-wise. The memory domain has many protocols such as SDRAM protocols (DDR5), SGRAM protocols (GDDR6), Memory Controller and PHY protocols (DFI), and others. The Cadence VIP Portfolio includes Memory Models that enable advanced verification of these protocols. The PE’s main role is to help accelerate VIP Portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a MM VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customers, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. The PE is expected to work independently and collaborate with other team members (R&D, Marketing, Customer Support, Field Teams) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel and cross-site collaboration over multiple geographies (Asia Pacific, Europe, US-East, US-South and US-West).

Job Responsibilities

• Leads projects with high resource, risk and/or complexity
• Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity
• Continually evaluates technology effectiveness/data interoperability of complex systems
• Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products
• Communicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view.

Experience and Technical Skills required

• At least 4 – 8 years of experience with Design and Verification
• Experience with Developing Verification environments using System Verilog
• Working knowledge and experience with the UVM methodology
• Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors.
• Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results.
• Excellent problem-solving and debugging skills
• Familiarity with Memory protocols is a must.
• Knowledge of the DFI protocol is a plus.

Qualifications

• BTech/BE/MTech/ME or equivalent with Electrical, Electronics & Comm or Computer Science Engineering

Behavioral skills required

• Must possess strong written, verbal and presentation skills
• Ability to establish a close working relationship with both customer peers and management
• Explore what’s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity

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