Lead SOC RTL Design Engineer

Roles and Responsibilities

· 9-12 years of solid experience in SoC IP design & SoC Subsystem Designs

· Experience with High Speed & Low Speed Protocol concepts

· Experience with SPI/I2C/I3C/UART/PWM all Low Speed IP’s and design

· Added advantage for experience in either UCIe/ Ethernet/ UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocol

· Experience in managing and lead teams of 4-5 Engineers

· Architectural level experienced with defining block, sub-system at SOC level

· Understanding of interconnect protocols like AXI/AHB/APB concepts

· Working knowledge of Lint, CDC, UPF, VCLP, DFT, Power and Clock Flow

· Good understanding of the design timing closure and verification debug

· Manage SoC dependencies, planning and tracking of all front-end design related tasks

· Should possess effective communication and leadership skills

Experience – 9 to 12 Years

Qualifications

• B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Skills and Qualifications

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.