Cadence

Lead Software Engineer - Compiler/LLVM

Ireland · Work style not stated · Full time

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About the role

Description from the employer’s posting. Check the employer’s page for the current version.

EmployerCadence
LocationIreland
Work styleWork style not stated
Employment typeFull time
Employer posted28 May 2026

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: LeadSoftware Engineer – Compiler/LLVM

Location: Cork, Ireland or Belo Horizonte, Brazil

Show full description

Reports to: Sr Software Architect

Job Overview:

Tensilica, a Cadence company, delivers configurable processor IP and DSP solutions powering AI, vision, audio, and communications workloads. Its Xtensa® architecture enables highly optimized, domain-specific designs with industry-leading performance and efficiency.

The C Compiler team builds the toolchain that unlocks this performance. Working on LLVM-based compilers for Xtensa processors, the team drives code generation, architecture-aware optimizations, and real-world workload performance.

In close partnership with hardware teams, they enable new capabilities and deliver production-grade tools used by leading semiconductor and systems companies.

Responsibilities:

Design and implement compiler optimisations and features for Xtensa processors
Drive improvements in code generation, performance tuning, and architecture enablement across the toolchain
Partner closely with hardware and architecture teams on new ISA features and capabilities
Analyse and optimise real‑world workloads, including AI, DSP, and vision use cases
Provide technical mentorship to junior engineers and contribute to the team’s technical direction and best practices

Requirements:

Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field (or equivalent practical experience)
Typically 4+ years of experience in compiler development or low‑level systems software (academic or industry experience considered)
Strong C/C++ programming skills with solid debugging and problem‑solving expertise
Good understanding of compiler internals (LLVM, GCC, or similar frameworks)
Strong foundation in computer architecture and performance optimisation

Nice to Have:

Experience with DSPs, AI/ML workloads, or embedded systems
Hands‑on experience with LLVM or GCC backends and optimisation passes
Experience working close to hardware teams or enabling new processor architectures

Check what we can offer you:

Competitive salary
25 days holiday per year
Private Medical and Dental plans, Income Protection and Life Insurance
Group Personal Pension Plan
Cycle to work scheme and gym subsidy
5 days paid time to volunteer to give back to our communities
Employee Stock Purchase Plan
The opportunity to work for a Great Place to Work© & Fortune 100 organization

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We’re doing work that matters. Help us solve what others can’t.

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