Logic Lead

The Logic Lead drives the architectural design and FPGA implementation of next-generation wireless protocol analyzers. You will lead the development of digital logic on high-end FPGAs to capture, demodulate, and process high-speed RF signals for Bluetooth and other wireless standards.

Key Responsibilities:

Architecture & Design

• Define FPGA architecture for protocol filtering, deep packet inspection, and capture engines.
• Design RTL for hardware accelerators, high-speed bus interfaces, and external memory controllers.
• Implement demodulators and decoders for Bluetooth (LE, Classic) and proprietary protocols.
• Optimize FPGA resources to maximize timing closure, throughput, and clock frequencies.

Leadership & Collaboration

• Lead engineers through the complete FPGA development lifecycle from concept to hardware timing closure.
• Collaborate closely with RF boards, software drivers, and system validation teams.
• Mentor junior and mid-level digital design and FPGA implementation engineers.
• Drive code reviews to maintain high-quality RTL and synthesis standards.

Verification & Testing

• Work with verification teams to build robust simulation and UVM testbench environments.
• Debug hardware issues on live FPGAs using Vivado ILA, SignalTap, or external logic analyzers.
• Support system integration to validate hardware co-design with software APIs.

Required Qualifications:

Technical Experience

• Education: Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• Experience: 8+ years in digital RTL design with a strong focus on FPGA deployment.
• Languages: Expert-level mastery of SystemVerilog, Verilog, or VHDL.
• FPGA Platforms: Deep knowledge of high-performance AMD Xilinx (UltraScale+, Versal) or Intel Altera (Stratix/Agilex) architectures.

Domain Knowledge

• Wireless Protocols: Deep understanding of Bluetooth (BR/EDR/LE) physical and link layers.
• Interfaces: Experience with high-speed transceivers (GTY/GTY), PCIe, USB 3.0, and DDR4/DDR5 memory interfaces.
• DSP Fundamentals: Familiarity with digital filters, mixers, and FFTs implemented in FPGA fabric.

Preferred Skills

• Experience building commercial test, measurement, or wireless sniffing equipment.
• Expertise in advanced timing closure techniques for high-utilization FPGA designs.
• Familiarity with Python, C/C++, or MATLAB for hardware modeling and automated testing.

Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.

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