Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization.

Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.

Required experience

• Worked on Subsystem / SOC level verification projects
• Experience in ARM based designs.
• In-depth knowledge SV-UVM
• Expertise in architecting, design and development of scalable verification environments from scratch. Define verification architecture and verification strategy
• Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals
• Experience in C based testcase development
• Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
• Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
• Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems
• Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
• Experience in mentoring junior engineers
• Self-driven and committed individual who can work in a fast paced project environment