Cadence

Principal Design Engineer

India · Work style not stated · Full time

Posted over 6 months ago: check it’s still open

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About the role

Description from the employer’s posting. Check the employer’s page for the current version.

EmployerCadence
LocationIndia
Work styleWork style not stated
Employment typeFull time
Employer posted6 Feb 2026

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality. The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies.

Show full description

This includes but is not limited to:

Digital architecture that has an understanding of the trade-offs for power, performance, and area

Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process

Understanding of synthesis, constraint generation, power management and DFT

Understanding of low-power designs and features (power islands, state retention, isolation)

Work with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation

Familiarity with uC Based subsystems and their architecture

Qualifications

7+ Years’ experience in working with Digital Design and Architecture.

Must have good written and verbal cross-functional communication skills.

Proven experience in most of the following:

Design Architecture

Design implementation

Embedded uC Designs

Synthesis and SDC Creation

Scripting of design automation

Debugging verification test cases / SVA’s to cover the design

Knowledge of existing Serial standards such as PCIE, USB, Ethernet, etc.

Must be comfortable interacting across the IPG development team including the ability to work with Mixed-signal, Verification and Analog teams

Knowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus

Working knowledge of revision control tools such as Perforce, Git, SVN is a plus

Education Level: Bachelor's Degree (MSEE Preferred)

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