Principal Digital Verification Engineer

• You will be expected to quickly understand the architecture and functional requirements of the project in order to effectively communicate and collaborate with systems engineers and architects.
• You will be responsible for the complete and detailed validation of entire subsystems by using an appropriate combination of simulation, formal and coverage methods.
• You will be responsible for creating, reviewing and optimizing simulation environment components, test case scenarios as well as functional coverage and formal verification test plans.
• You will be expected, if/when appropriate, to lead focused groups of individuals or mentor individuals and manage their priorities towards reaching a specific set of objectives
• You will be accountable for estimating schedules, and once approved track them towards timely completion, while providing clear and precise status updates at regular intervals
• Possibility of reporting directly to the Senior Manager as an ASIC Verification Prime

• As an ASIC verification Prime, you would be responsible for all aspects of the verification of the digital portion of the Serdes as well as working with partner teams to ensure overall Serdes coverage.
• You would also be responsible for participating in architectural and design reviews to proactively advise on verification impacts and improvements for schedule and or coverage.

The Must Haves:

• Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with expert level experience in the use of System Verilog, UVM, SVA, and simulators from major vendors.
• Proven ability in determining appropriate and comprehensive digital verification and coverage strategies
• Highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically address (debug) sophisticated technical problems.
• Excellent organization, written and oral English communication skills.

Assets:

• Experience with

• Formal verification methods
• DSP and/or Forward Error Correction
• Using Jira for bug tracking and GIT for source code management and revision tracking

• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.

The annual salary range for this position is $147,100 - $234,900.

#LI-BH #LI-Onsite

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.