Principal Hardware Application Engineer

* Schematic and layout review: Review customer PCB schematics and layout files for Marvell DC switch platforms. Provide design guidance on component selection, power sequencing, clock distribution, and high-speed signal routing.

* SI/PI analysis: Perform or coordinate signal integrity and power integrity simulations (pre- and post-layout) for high-speed Ethernet interfaces at 800G, 1.6T, and beyond. Evaluate channel performance, SerDes tuning (Tx EQ / Rx CTLE), and PAM4 link margin.

* Board bring-up and debug: Support hardware bring-up at customer sites and in Marvell's Taipei lab. Debug L1 issues including SerDes link training, power integrity, thermal, and interface failures.

* Design documentation: Author and review hardware design guides, application notes, schematic checklists, and layout guidelines for internal and external use.

* Cross-functional collaboration: Join-in EE/ME/SI/PI design reviews with Marvell's global hardware engineering team. Represent customer requirements and feed back design insights to silicon and platform teams.

* Technology exploration: Ramp up knowledge on next-generation interconnect technologies including UALink, ESUN, CPO (Co-Packaged Optics), and 224G SerDes. Contribute to internal training and knowledge-sharing forums.

* Supplier chain engagement: Leverage Taiwan's comprehensive supply chain ecosystem — PCB materials, thermal solutions, power components, connectors, and cabling — to optimize platform designs.

What We're Looking For

Basic Qualifications:

Bachelor's degree or above in Electrical Engineering, Electronics Engineering, or a related field

8+ years of experience in hardware design or hardware application engineering for high-speed networking or data center systems

Proficiency in EE design tools: schematic capture (e.g., Cadence OrCAD, Mentor PADS, or equivalent) and PCB layout review (e.g., Cadence Allegro or equivalent)

Solid knowledge of signal integrity (SI) principles for high-speed differential interfaces: understanding of channel loss, eye diagram analysis, SerDes Tx/Rx equalization, and PAM4 link budget

Familiarity with power integrity (PI) concepts: PDN design, AC/DC simulation, decoupling strategy, and power sequencing

Experience supporting customers through the hardware design cycle: schematic review, layout review, bring-up, and EDVT

Strong communication skills — able to present technical findings clearly to both engineering teams and customer stakeholders

Proactive, self-driven working style with the ability to manage multiple customer engagements in parallel

Preferred Qualifications:

Hands-on experience with DC switch or high-speed Ethernet platforms (e.g., 400G, 800G, 1.6T switch designs)

Familiarity with Marvell Teralynx (TL7, TL10, T100) or equivalent DC switch silicon

Experience with SI/PI simulation tools (e.g., Sigrity, Ansys SIwave, HFSS, PowerDC or equivalent)

Knowledge of next-generation interconnect technologies: UALink, ESUN, CPO, or 224G SerDes

Knowledge with thermal design considerations for high-power switching platforms (air cooling, liquid cooling)

Familiarity with MSDC (Microsoft, AWS, Google, Meta) ODM design requirements and supply chain ecosystem in Taiwan

Experience with board bring-up tools: oscilloscopes, VNAs, BERT, and real-time sampling scopes


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.


Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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