Senior ASIC Design Engineer - Client IP

• As a senior digital design engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
• You will produce an implementation specification document and have it reviewed by your team, architects, analog designers if applicable
• You are accountable for the creation and integration of new and existing RTL code, algorithms and functions
• You are held responsible for designer testing of your code as well as debugging of your code during simulation and regression verification
• You will assist the verification team in determining coverage and provide design assertions and waivers as needed
• You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
• You will be involved in lab validation of the product and its prototype if applicable
• You are expected to report on status updates on a regular basis

The Must Haves:

• Electrical or computer engineering, or other applicable scientific degree at the BEng/BSc or MEng/MSc level
• Experience: 5+ years using System Verilog for design
• Experience: 5+ years running digital design synthesis, STA, timing closure and asynchronous clock crossings
• A highly motivated self-starter, able to work independently, while being a team player
• Ability to methodically solve complex technical problems
• Excellent organization, written and oral (English) communication skills
• Familiarity with digital (including formal) verification methods
• Good understanding of timing/power/area analysis and trade-offs

Assets:

• Experience with digital silicon design backend process
• Experience with digital design for low power
• Experience with standards and protocols such asOTN/FlexO/B100G, Ethernet (100GE+)
• Experience with usingGIT for source code management and revision tracking
• Experience with usingJira for schedule planning, assignment tracking and bug reporting
• Familiarity with programming languages such as Python, Make, bash.

The annual pay range for this position is $109,000 - $174,000 CAD.

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Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.