Senior ASIC Design Engineer

Your Responsibilities:

• Working in full ASIC design cycle ranging from micro architecture design, RTL coding, verification, synthesis, FPGA prototyping, and silicon bring-up.
• IP/SoC verification in C/C++, System Verilog, and UVM environment.
• Support of IP delivery, FPGA prototyping and silicon validation.
• Solving complex design and verification problems with your innovative ideas.

Your Profile Preferred:

• MSEE with 3+ years of experience with working knowledge in Bluetooth, IEEE 802.15.4, wireless or other networking controller design and implementation.
• Micro-architecture, Verilog RTL coding, and IP/SoC verification.
• Familiar with ASIC design concept and design flow: HW/SW co-simulation, synthesis, Lint/CDC, and formal verification.
• Fluent in C/C++, System Verilog, and UVM.
• Familiar with SVA assertion and coverage driven verification.
• Familiar with Perl, Python, shell script, and Tcl.
• Small area and low power design experience.
• SOC integration experience.
• Complete product cycle experience from specification to production.
• Hands-on lab experience on FPGA validation and post-silicon bring-up.
• Excellent communication and report documentation skills.

NXP’s Wireless Connectivity team has an open and inclusive work environment that promotes excellence, innovation, collaboration, and integrity. An expanding business comes with tremendous career opportunities which will challenge and grow your talents. If you are ready to start the next chapter of your career in the wireless area, you don’t want to miss this opportunity to join a world leader in this technology.

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