Senior Debug Validation Engineer

Reporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness.

This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage.

The Team

The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems.

The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure.

Responsibilities and Duties

• Lead post-silicon debug and validation activities for AI compute silicon and platform technologies
• Contribute to debug and validation activities across multiple projects and milestones
• Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones
• Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation
• Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency
• Collaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions
• Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions
• Develop and enhance automated debug, regression and validation infrastructure using Python and related technologies
• Analyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues
• Support development of validation tests, debug tooling and custom diagnostics to improve coverage and observability
• Define validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis
• Drive continuous improvement of debug processes, validation methodologies and engineering workflows
• Communicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders
• Support silicon readiness reviews and contribute to product quality and release decisions
• Contribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows

Candidate Profile

Essential:

• Strong experience in bare metal environments
• Good knowledge of SoC and platform architectures
• Expertise in debug infrastructure and post-silicon debug methodologies
• Strong programming skills in Python, C, or debug scripting languages such as CMM
• Highly motivated self-starter with a collaborative and team-oriented approach
• Ability to work across teams and programming languages to identify root causes of deep and complex issues
• Experience of the post-silicon validation process applied in digital ASIC environments
• Strong Linux and Python experience
• Exceptional communication skills and the ability to collaborate effectively to solve complex problems
• Excellent problem-solving, analytical and diagnostic skills
• Deep knowledge of scan, DFT, JTAG and trace infrastructure
• Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques
• Ability to work independently on technically complex debug and validation activities across hardware, firmware and software domains

Desirable

• Understanding of DFT flows from insertion through post-silicon validation
• Experience developing tooling for parsing and analysing debug data, including scan dump parsing
• Driver-level experience with one or more of the following technologies:

• PCIe
• Ethernet
• Memory technologies including LPDDR, DDR and HBM
• Peripheral interfaces such as I2C, I3C and SPI

• Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM
• Good knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols
• Experience with Arm CPU architectures, system IP and associated debug tooling
• Experience with AMBA protocols
• Understanding of ML applications and associated workloads
• Experience in characterization, failure analysis, test development, statistical analysis and customer support