Allegro MicroSystems

Senior Digital Verification Engineer

Czechia · Work style not stated · Full time

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About the role

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EmployerAllegro MicroSystems
LocationCzechia
Work styleWork style not stated
Employment typeFull time
Employer posted2 Oct 2026

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.

About the Role

Allegro MicroSystems is seeking a Digital Verification Engineer to join our team developing next-generation magnetic position/current sensors, motor drivers, and power management ICs. You will be responsible for verifying complex digital and mixed-signal designs, ensuring first-pass silicon success for products that drive e-mobility, clean energy, automation, and robotics forward.

Key Responsibilities

Develop and execute verification plans for digital and mixed-signal IP and full-chip designs.
Build and maintain constrained-random, coverage-driven testbenches using SystemVerilog and UVM.
Define functional coverage, assertions (SVA), and checkers to measure and close verification goals.
Perform block-level, subsystem, and top-level (full-chip) verification, including analog/digital interaction using Verilog-AMS / real-number modeling.
Debug failures in collaboration with RTL designers, analog designers, and firmware teams.
Contribute to regression setup, automation, and continuous-integration verification flows.
Track and report coverage closure, bug metrics, and sign-off readiness.
Participate in design and verification reviews.

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Required Qualifications

Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering (or equivalent).
Strong proficiency in SystemVerilog and the UVM methodology.
Solid understanding of digital design fundamentals, RTL (Verilog/VHDL), and synthesis concepts.
Experience with constrained-random, coverage-driven verification and assertion-based verification (SVA).
Proficiency with industry simulation/debug tools (e.g., Cadence Xcelium/SimVision, Synopsys VCS/Verdi, or equivalent).
Scripting skills (Python, Perl, Tcl, or shell) for automation and flow development.
Strong problem-solving, debugging, and communication skills.

Preferred / Nice-to-Have

Experience with mixed-signal verification (Verilog-AMS, real-number modeling / wreal).
Familiarity with functional safety (ISO 26262) and/or automotive quality (AEC-Q100) requirements.
Exposure to formal verification methods and tools.
Experience with low-power verification (UPF/CPF).
Knowledge of sensor, motor driver, or power management IC architectures.
Experience with version control (Git) and CI/CD for verification regressions.

Why Allegro?

Join Allegro and become part of a team where your contributions truly matter.

We foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.
Your work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.
You’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.
Join us—and help build what’s next.

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