Axiado

Senior / Lead Physical Design Engineer

Hyderabad, TS, India · On-site · Full-time

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About the role

Description from the employer’s posting. Check the employer’s page for the current version.

EmployerAxiado
LocationHyderabad, TS, India
Work styleOn-site
Employment typeFull-time
Employer posted2 months ago

We are looking for a highly experienced and hands-on Senior / Lead Physical Design Engineer to drive backend implementation, signoff quality, methodology development, and project execution across our ASIC programs.

This role combines technical leadership with hands-on execution. The successful candidate will be responsible for defining implementation strategies, establishing Physical Design and Physical Verification methodologies, reviewing and guiding work performed by contractors and external vendors, and ensuring successful execution from RTL handoff through tapeout.

The ideal candidate is a strong shift-left thinker who can proactively identify implementation risks, influence architectural decisions, and drive scalable solutions while remaining deeply involved in technical problem solving.

Key Responsibilities

Technical Leadership & Project Execution

Show full description

Lead Physical Design activities from project planning through tapeout.

Define implementation strategies, milestones, and execution plans.

Work closely with contractors, consultants, and external implementation partners to ensure high-quality deliverables.

Review implementation progress, identify risks, and drive corrective actions.

Provide technical leadership across Physical Design, STA, DFT, RTL, and CAD teams.

Drive design reviews and implementation readiness reviews.

Physical Design Ownership

Own block and full-chip implementation activities including:

Floorplanning

Power Planning

Placement

CTS

Routing

Timing Closure

ECO Implementation

Signoff Closure

Drive performance, power, area, congestion, and timing optimization.

Physical Verification & Signoff

Define and drive signoff methodology and closure strategy.

Lead DRC, LVS, ERC, Antenna, Density, and Manufacturing rule closure.

Review and sign off vendor deliverables related to physical verification.

Debug complex signoff issues and drive root-cause resolution.

Methodology & Flow Development

Develop and improve Physical Design methodologies, implementation recipes, and signoff flows.

Drive automation initiatives to improve productivity and design quality.

Establish best practices, checklists, and execution guidelines across projects.

Promote shift-left methodologies to improve backend predictability and reduce project risk.

Cross-Functional Collaboration

Partner with Architecture, RTL, DFT, Verification, Packaging, CAD, and Product teams.

Influence design decisions through implementation-aware feedback.

Drive early risk identification and mitigation planning.

Support customer, vendor, and management reviews when required.

Required Qualifications

BS/MS in Electrical Engineering or related field.

8–12 years of ASIC Physical Design experience.

Multiple successful tapeouts in advanced technology nodes.

Strong experience owning implementation from RTL handoff through GDS signoff.

Experience leading projects, reviewing deliverables, and coordinating work across multiple stakeholders.

Strong Expertise In

Floorplanning & Hierarchical Planning

Power Planning

Placement & Optimization

CTS & Clock Architecture

Routing & Signal Integrity

STA & Timing Closure

ECO Methodologies

MCMM Flows

Power Optimization

Low Power Design Techniques

Physical Verification Expertise (Must Have)

Strong hands-on experience with:

Calibre

IC Validator (ICV)

Expertise in:

DRC

LVS

ERC

Antenna

Density Closure

Physical Signoff

Ability to independently debug and resolve complex signoff issues.

Preferred Qualifications

Experience managing or mentoring junior engineers, contractors, or external vendors.

Strong Tcl and Python scripting skills.

Experience developing implementation methodologies and signoff frameworks.

Experience with advanced nodes (7nm/5nm/3nm and below).

Familiarity with low-power implementation and UPF flows.

Experience with package-aware floorplanning and bump planning.

All your information will be kept confidential according to EEO guidelines.

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