Senior Manager, Design Verification Engineering

About ADI:

Analog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.

About the Role

Lead design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI. The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.

Responsibilities

• Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.
• Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.
• Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.
• Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.
• Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.
• Develop and execute end-to-end system-level use cases for comprehensive functional validation.
• Architect and implement scalable UVM-based testbenches, DV flows, and methodologies.
• Define and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.
• Work cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.
• Apply formal verification techniques for IP and subsystem-level validation.
• Lead NoC/interconnect verification and ensure robust data flow across the SoC.
• Perform performance verification and system-level analysis across real-world use cases.
• Drive innovation in verification strategies to meet aggressive schedules and quality goals.
• Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.

Requirements

• B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.
• Strong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
• Proven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.
• Expertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.
• Experience in architecting scalable testbench environments and defining robust DV flows and methodologies.
• Strong background in power-aware verification (UPF), including power analysis and optimization.
• Hands-on experience with formal verification, including flow definition, connectivity, and functional property checking.
• Solid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.
• Experience in security and safety verification, ensuring compliance with secure design and functional safety requirements.
• Familiarity with gate-level simulations with timing annotation (GLS).
• Strong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.
• Good understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).
• Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.
• Excellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.
• Strong problem-solving mindset with the ability to quickly learn and adopt new technologies

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days