Senior / Staff ATE Test Engineer – Optical Transceiver Silicon

What you'll do

Own the test strategy for one or more ICs: coverage plan, test list, insertion flow (wafer sort, final test, system-level).

Develop, debug, and optimize ATE test programs for mixed-signal and high-speed devices — analog and DC parameters, high-speed signal path, on-chip test points, digital scan, and firmware-driven test modes.

Specify and bring up test hardware: load boards, probe cards, socketing, and the opto-electrical fixturing our photonics-attached parts require. Work with vendors through layout, fab, and first article.

Drive first-silicon bring-up alongside design and validation. Correlate ATE results to bench characterization and to system-level performance, and close the loop when they disagree.

Own the relationship with our OSATs and test houses in the region: program release, correlation across testers and sites, multi-site and throughput optimization, capacity planning, and day-to-day production support.

Analyze sort and final test data to find yield limiters, marginal tests, and guard-band problems. Lead failure analysis and root cause on returns and excursions.

Set the standard for how test is done here — reusable test IP, data infrastructure, documentation, and review practice — and mentor junior test engineers as the Singapore team grows.

What we're looking for

BS/MS in Electrical Engineering, Computer Engineering, Physics or a related field.

8+ years developing production test for mixed-signal or high-speed ICs, including at least one program taken from first silicon through to high-volume production.

Deep hands-on ATE experience on at least one major platform (Advantest 93K or T2000, Teradyne UltraFLEX or J750, Eagle, Chroma, or comparable).

Strong programming: C/C++ and Python, on Linux. You write test code other engineers can read and extend.

Solid analog and mixed-signal fundamentals — you can read a schematic, reason about a datasheet spec, and design the measurement that proves it.

Practical test hardware skills: load board and probe card design review, signal integrity at speed, bench instrumentation (scopes, BERTs, SMUs, network analyzers, VNAs), and lab debug.

Statistical fluency for yield and correlation work — JMP, MATLAB, Python/pandas, or equivalent.

Direct experience running programs at OSATs and managing external test partners.

Willingness to travel regionally to test sites, and to overlap with US and India hours when a bring-up or an excursion calls for it.

Preferred Qualifications

Established working relationships with OSATs and test houses in Singapore, Malaysia, Taiwan, or the Philippines.

High-speed SerDes test experience at 100G/lane and above: BER, jitter decomposition, eye margining, loopback methods.

Silicon photonics, optical transceiver, or opto-electrical test background — coupled-fiber test, optical power and wavelength measurement, TIA and driver characterization.

DFT familiarity: scan, MBIST, JTAG/IEEE 1149, on-chip instrumentation and monitors.

STDF and test data pipelines; building analytics that engineers actually use.

Experience defining test for a product line in its first generation, where nothing existed yet.

Why this role

Optical I/O for AI is being defined right now, and test is one of the places where it is won or lost — a part that cannot be screened economically does not ship, however good the design. You will have real authority over test architecture on silicon going into production at scale, short lines to the designers who can change the chip, and a founding hand in how our Singapore silicon team is built.