Senior / Staff Design Verification Engineer

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Job Description:

We are seeking a highly skilled and motivated Senior Design Verification Engineer with over 5 years of experience to join our silicon engineering team. In this role, you will play a critical part in ensuring the functional correctness of complex, next-generation SoCs/IPs. You will be responsible for the entire verification lifecycle—from scoping and test plan creation to architecture development, debugging, and achieving 100% coverage closure.
The ideal candidate possesses rock-solid verification fundamentals, deep expertise in System Verilog (SV) and UVM, and a proven track record of delivering tape-out-ready designs.

Key Responsibilities

• Testplan Ownership: Review architectural and micro-architectural specifications to define, architect, and author comprehensive, feature-driven verification plans (testplans).
• Environment Development: Design, build, and maintain scalable, reusable, and robust constrained-random verification environments from scratch using SystemVerilog (SV) and the UVM methodology.
• Verification Strategy: Define effective verification strategies at the block, sub-system, and/or SoC level, incorporating both simulation and formal techniques where applicable.
• Debugging & Triage: Efficiently debug complex test failures, identify RTL or testbench defects, and collaborate closely with Design and Architecture teams for rapid resolution.
• Coverage & Sign-off: Define, implement, and analyze functional (covergroups, coverpoints, crosses) and code coverage. Drive the verification closure process to achieve 100% coverage targets.
• Mentorship: Provide technical guidance and mentorship to junior verification engineers, participating in code and testplan reviews to maintain high engineering standards.

Required Skills & Qualifications
Experience

• 5+ years of dedicated experience in ASIC/SoC Design Verification with bachelors or master's in ECE, EEE, Embedded Systems, VLSI

Technical Competencies

• Core Fundamentals: Strong understanding of digital logic design, computer architecture, FIFO, pipelines, memory controllers, and clock/reset domains.
• Languages: Advanced proficiency in SystemVerilog (SV) and Object-Oriented Programming (OOP) concepts.
• Methodology: Extensive, hands-on experience with UVM (Universal Verification Methodology) including writing sequences, drivers, monitors, scoreboards, and predictors.
• Coverage Closure: Proven track record of writing complex functional coverage models and successfully closing both code and functional coverage.
• Debugging: Mastery of industry-standard debugging tools (e.g., Verdi, DVE) and a methodical approach to root-causing complex RTL/TB bugs.
• Protocols: Familiarity with standard on-chip protocols (e.g., AXI, AHB, APB, PCIe, NVMe, USB, or Ethernet) depending on the specific team focus.
• Scripting: Experience with scripting languages (Python, Perl, or Tcl) and Shell scripting to automate verification workflows.

Soft Skills

• Excellent analytical and problem-solving skills.
• Strong communication skills with the ability to collaborate effectively across cross-functional teams (Design, Architecture, and Validation).
• Self-motivated with a strong sense of ownership and attention to detail.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.