Senior System Level Verification Engineer

Has worked through complete project cycle of an SOC ASIC chip

Thorough understanding of CPU and its debug architecture, as well as SOC system architecture

Proficient in programming and modeling typical SOC connected devices, such as JTAG, UART, SPI, I2C.

Proficient in testplanning, test case development using C, and self checking in such tests

Proficient in RTL debugging using waveform viewer

Mastery in C programming, and fluent in scripting languages such as Make, Python, Perl and shell script

Fluent in documentation and issue tracking using Confluence and Jira tools

Preferred experience in

Validation on emulation, FPGA and post-silicon

Complex IP interface validation of USB, Ethernet, PCIE, DDR

Using AI tools in testplanning, generation and debugging

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.