Silicon Physical Design Engineer

For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to take ownership of their designs and problem solutions. You will become part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure.

The Team

The physical design team sits within the wider silicon design team which includes RTL, verification and DFT and with whom we collaborate extensively. Our work additionally involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and then to build the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC).

Responsibilities and Duties

Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs in leading-edge process technologies while meeting ambitious development schedules. Contributions are expected to span multiple areas and involve:

• using state-of-the-art EDA tools and in-house Graphcore flows to deliver final designs that are of sign-off quality
• enhancing existing flows and in-house tools/APIs to support new features and/or methodologies
• analysis and/or debugging of complex engineering problems leading to workable solutions
• developing an understanding of emerging technical issues and applying that knowledge to optimise in-house flows and methodologies

Candidates will be expected to work closely both with other teams within Graphcore and with 3rd party support engineers/contractors, ensuring good communication between all parties, and to contribute meaningfully to the overall efficiency and success of the Physical Team.

Candidate Profile

Essential Skills and Experience:

• A Degree in Electronic/Electrical Engineering, Computer Science or related subject
• Be highly motivated, a self-starter, and a team player
• Enjoy taking responsibility and improving skills and knowledge
• Excellent problem-solving skills for debugging issues seen and finding root causes
• Ability to program/script (required to solve design issues, typically in Tcl and Python)
• Experience in 7nm or smaller technologies
• A good breadth of experience with physical design flows including: Floorplanning/Budgeting, Synthesis, Place and Route, Clock CTS, Timing Analysis, Logical Equivalence, Physical Verification (DRC/LVS/ERC)

Desirable Skills and Experience:

• In depth expertise in one or more aspects of physical design flows
• Structuring of builds to maximise PPA
• Silicon transistor knowledge including std cell libraries and/or memories
• 2D and 3D design (CoWoS, UCIe etc.)
• High speed, high power and/or full reticle chip design
• Ethernet, PCIe, LPDDR, HBM interfaces
• Power integrity and optimization
• 2nm or 3nm technologies
• Chip finishing (pad rings, chip level LVS/DRC/ERC)
• Design for test
• Team management
• Project Planning

Benefits

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments