Sr Engineer, Low Power Verification & Formal Equivalence

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Job Description:

About the Role

We are seeking a highly skilled Senior Engineer to drive our Low Power Verification and Formal Equivalence signoff execution. In this critical role, you will take ownership of static low power checks and formal verification flows for our advanced, high-performance design blocks and sub-systems. You will partner closely with Physical Design and Power teams to ensure robust power intent implementation and flawless logical equivalence throughout the RTL-to-GDSII flow, including executing complex, late-stage engineering changes (ECOs).

Key Responsibilities

Low Power Signoff Execution: Take ownership of static low power verification checks across assigned design blocks and sub-systems, ensuring complete coverage and zero low-power structural bugs.

UPF Implementation & Automation: Deploy, optimize, and maintain Unified Power Format (UPF) coding and verification flows, collaborating with architecture and methodology teams to ensure alignment with platform standards.

Formal Equivalence Ownership: Own and drive the Logical Equivalence Checking (LEC) flow for your design blocks, ensuring strict logical equivalence from RTL through post-route netlists, including the execution of complex functional ECOs.

Cross-Functional Collaboration: Apply your understanding of Physical Design constraints and power architectures to debug violations and provide optimal, implementable UPF and equivalence solutions alongside backend teams.

Required Qualifications

Education & Experience: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 3+ years of relevant industry experience in ASIC/SoC design and verification.

Power Intent Proficiency: Strong, practical experience coding, debugging, and maintaining power intent using the Unified Power Format (UPF).

Static Power Verification: Proven expertise running, analyzing, and debugging static low power checks on both RTL and post-PNR netlists using industry-standard tools (e.g., Synopsys VC Low Power / VCLP).

Formal Signoff: Hands-on experience with Logical Equivalence Checking (LEC) and Formal Equivalence tools (e.g., Synopsys Formality), including experience implementing and verifying formal ECO flows.

Low Power Libraries: Technical understanding of Power Management library cells and their physical/logical implications, including Isolation cells (ISO), Level Shifters (LS), Always-On (AON) cells, and Retention registers.

Preferred Qualifications

Physical Design Foundation: Solid foundational knowledge of the backend Physical Design (PD) flow, enabling you to anticipate implementation challenges and bridge the gap between frontend intent and backend realization.

Scripting & Automation: Strong scripting proficiency (Tcl, Python, or Perl) to drive flow automation, parse log files, and implement methodology improvements.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.