Sr. Engineer, SoC Design Verification

This role is hybrid, based out of Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification.
• Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug.
• Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement.
• Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios.
• Proactive, detail-oriented, and effective in cross-functional technical discussions.
• Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools.

What We Need

• Develop and own scalable verification environments for Beowulf SoC CSS, DDR, and Fabric NoC across subsystem and full-SoC levels.
• Write, refine, and execute test scenarios for compute operation, memory initialization and traffic, coherency, routing, ordering, QoS, power management, error handling, and data movement.
• Analyze coverage gaps, debug failures, drive root-cause analysis, and collaborate closely with architecture, RTL, firmware, emulation, and system teams.
• Drive verification planning, regression quality, coverage closure, and signoff for major SoC features.
• Automate verification flows using scripting, reusable infrastructure, and AI productivity tools.
• Mentor engineers and contribute to verification methodology and design-for-verification improvements.

What You Will Learn

• In-depth SoC verification across compute, DDR, coherency, and Fabric NoC using modern workflows, tooling, and scripting.
• Integration of pre-silicon SoC verification with emulation, silicon bring-up, and platform validation strategies.
• How AI-driven automation reshapes modern DV workflows.
• Exposure to high-performance, system-level verification in advanced AI SoC designs.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.