NXP

Sr. Lead ASIC design Engineer - Digital Design

India · Work style not stated · Full time

Posted over 6 months ago: check it’s still open

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About the role

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  • EmployerNXP
  • LocationIndia
  • Work styleWork style not stated
  • Employment typeFull time
  • Employer posted
  • Key Responsibilities
  • Define and implement hardware architectures optimized for AI inference SOC's
  • Contribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO's
  • Own features end-to-end: specification → RTL → integration → synthesis → debug
  • Collaborate with physical design teams on synthesis, timing closure, and power optimization.
  • Collaborate with verification team to ensure design correctness.
  • Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.
  • Required Qualifications
  • 7+ years of experience in ASIC/SoC RTL design
  • Strong Verilog/SystemVerilog coding skills
  • Solid understanding of synthesis, timing, and power analysis
  • Experience with Lint/CDC/RDC flows
  • Strong debugging and root-cause analysis capability
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At a glance

  • Employment typeFull time
  • SeniorityLead / Principal
  • Employer posted
  • Added to ROLIVA
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