Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING

Essential ​Responsibilities:

Technical Leadership

• Lead the end-to-end development of processor cores, subsystems, from architectural specification through tapeout.
• Drive microarchitecture definition and RTL implementation for high-performance and low-power processor designs.
• Review design specifications, RTL quality, synthesis results, timing closure strategies, and integration readiness.
• Ensure design compliance with functional, performance, power, reliability, and security requirements.
• Guide architectural tradeoff analysis and performance optimization activities.
• Establish and enforce design methodologies, coding guidelines, and best practices.

Program Execution

• Develop project plans, resource allocation strategies, and execution schedules.
• Track design milestones, identify risks, and implement mitigation plans.
• Drive design reviews, signoff readiness, and cross-functional execution alignment.
• Ensure successful delivery of processor IP and SoC projects within schedule and quality targets.
• Coordinate with global engineering teams and external partners where applicable.

Team Leadership & People Management

• Build, mentor, and lead a high-performing processor design team.
• Define career development plans and coaching programs for engineers.
• Recruit and retain top engineering talent.
• Conduct performance discussions and support succession planning.
• Foster a culture of technical excellence, innovation, collaboration, and accountability.

Other Responsibilities:

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications:

• Bachelor's or master's degree in Electronics Engineering, Computer Engineering, Electrical Engineering, or related field.
• Minimum of 12+ years (Senior Manager) of experience in digital IC/SoC/processor design.
• Strong expertise in:

• Microarchitecture development
• RTL design (Verilog/SystemVerilog)
• Processor pipelines and memory subsystems
• SoC integration
• ASIC design flow
• Synthesis and timing analysis

• Proven track record of successful silicon delivery.
• Experience leading medium to large engineering teams.
• Strong understanding of PPA optimization techniques.
• Excellent communication, leadership, and stakeholder management skills.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science
• Experience with RISC-V, MIPS, ARM, ARC, or custom processor architectures.
• Experience with advanced technology nodes (7nm, 5nm, 3nm, and beyond).
• Expertise in multicore processors, AI accelerators, or high-performance computing architectures.
• Experience leading geographically distributed teams.
• Strong written & verbal communication skills.
• Strong planning & Organizational skills.

Expected Salary Range

$167,000.00 - $275,000.00

The exact Salary will be determined based on qualifications, experience and location.

If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.

An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.

All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law