Sr. Packaging Engineer (Semiconductor)

· Failure Analysis & Yield Support: Perform systematic failure analysis of package-related defects — including die cracking, chipping, delamination, wire bond lift, and interconnect degradation — and help implement corrective actions to improve yield and long-term product reliability. (10%)

· Cross-Functional Collaboration: Partner closely with IC design, process engineering, product engineering, and test teams to ensure package constraints and parasitics are accounted for early in the product development cycle, and provide packaging input to NPI planning and tape-out reviews. (10%)

· Package Simulation & Characterization: Conduct package-level electrical and thermal simulations to optimize package performance for high-current transient protection applications, and validate simulation results through characterization and bench testing. (10%)

· Technology Roadmap Support: Contribute technical input to the advanced packaging technology roadmap owned by the principal packaging engineer, helping identify emerging packaging technologies, materials innovations, and cost reduction opportunities to sustain competitive differentiation in the TVS, TDS, and Hot Switch markets. (10%)

· Documentation & Standards: Author and maintain comprehensive packaging specifications, process control documents, design rule guidelines, and qualification reports, ensuring full traceability and compliance with internal quality systems and customer-specific requirements. (10%)

Minimum Qualifications:

• Education

· Bachelor's degree in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a closely related field is required; Master's degree or PhD preferred.

• Experience

· Minimum of 5 years of progressive experience in semiconductor packaging engineering, with a demonstrated track record of increasing technical responsibility.

· Demonstrated hands-on experience with advanced package formats relevant to discrete protection devices, including WLCSP, DFN, QFN, SOD, SOT, and flip-chip assemblies.

· Direct experience working with OSAT partners in a technical capacity, including process development, design rule definition, and supplier qualification activities.

· Proven experience executing JEDEC and AEC-Q101 reliability qualification programs, including test plan development, data analysis, and formal qualification reporting.

• Technical Skills

· Deep understanding of semiconductor assembly processes including wafer dicing, die attach, wire bonding, molding, plating, and wafer-level packaging processes such as WBC (wafer backside coating) and CDAF.

· Proficiency in failure analysis techniques including cross-sectioning, SEM/EDX, SAT (scanning acoustic tomography), and optical microscopy.

· Working knowledge of package-level electrical and thermal simulation tools.

· Familiarity with statistical process control (SPC), CPK analysis, and DOE methodologies as applied to packaging process development.

· Understanding of ESD, TVS, and protection IC device physics and how package parasitics influence transient protection performance.

• Soft Skills & Other Requirements

· Strong technical communication skills with the ability to present complex packaging topics to both engineering peers and executive management.

· Ability to work effectively in a cross-functional, globally distributed team environment spanning design, manufacturing, quality, and commercial organizations.

· Willingness to travel domestically and internationally to OSAT and fabrication partner sites as needed