Cadence

Sr Principal Design Engineer

India · Work style not stated · Full time

Posted over 6 months ago: check it’s still open

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About the role

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EmployerCadence
LocationIndia
Work styleWork style not stated
Employment typeFull time
Employer posted12 Jan 2025

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Sr Principal Design Engineer

Location: Noida

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Show full description

Job Summary:

The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers. The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions. The role will require customer interactions including pre and post-sales activities, DV methodology review and customer support.

Job responsibilities:

Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics.

Participate in Technical alignment with verification experts in defining verification strategy, architecting verification environment.
Represent DV and technically work/lead team interactions with RTL, Subsystem and Performance for design verification tasks.
Contribute towards defining, developing, and deploying new functional verification methodologies.
Participate in interactions with Marketing, AE and Release team when required.
Review project signoff and quality of DDR controller feature verification.

Experience and Technical Skills required:

At least 11+ years of relevant experience including design verification experience.
Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
Strong expertise in Verilog, SV with UVM methodology.
AXI and/or CHI experience is highly desirable.
Prior experience in leading and managing teams with expertise in any of DDR, PCIe, UCIe or USB is strongly required.
Memory controller verification experience is a plus.

Qualifications

BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent

Behavioral skills required

Must possess strong written, verbal and presentation skills
Ability to establish a close working relationship with both customer peers and management
Explore what’s possible to get the job done, including creative use of unconventional solutions
Work effectively across functions and geographies
Push to raise the bar while always operating with integrity

We’re doing work that matters. Help us solve what others can’t.

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