Sr Principal Design Engineer — Memory Modeling Portfolio

The Team
The MMP R&D team develops and sustains a world-class memory model IP library spanning UFS/Unipro/MPHY/RMMI, SDRAM families (DDRx, LPDDRx, HBMx), NAND Flash, DFI PHY, and hybrid memory technologies. We are a globally distributed, deeply collaborative group — technically rigorous and genuinely invested in each other’s growth. The culture is one of mutual support, cross-training, and shared ownership of quality. Engineers here become true experts: in protocols, in verification methodology, and in the art of building trust with colleagues and customers. This candidate joins that team as a senior technical anchor in Korea, with visibility across the full global operation.

Responsibilities:

Serve as the primary customer interface for protocol integration, system-level debugging, and solutions consulting across the UFS/Unipro/MPHY/RMMI stack. Be present and effective on customer sites when the situation calls for it

Help customers debug, characterize, and articulate the root problem they are trying to solve — even when they don’t yet have the language for it — and translate those findings into clear, actionable problem definitions for the R&D team

Triage and analyze incoming field issues. Scope, disposition, and schedule repair of model defects in close coordination with R&D. Track issues through to resolution with accountability to both the customer and the team

Analyze customer requirements and map them to MMP product capabilities or feature gaps. Present proposed solutions with clarity to both technical and managerial audiences

Mentor and guide less experienced design engineers in protocol understanding, RTL code, and verification methodology. Serve as a reliable senior resource for peers as well as engineers at earlier career stages navigating the emulation and protocol terrain

Actively participate in the team’s development lifecycle — reviews, cross-verification, cross-training, quality processes — as a trusted technical contributor, not merely an observer

Review RTL implementation approaches developed by team members; provide technically grounded feedback that raises quality without stalling momentum

Partner with internal account and field teams globally to ensure customer success on complex memory model deployments. Build and sustain long-term, trust-based relationships with key customer contacts

Bring consistent energy, stability, and a genuinely collaborative spirit to a team that depends on those qualities as much as on raw technical skill

Job Qualifications:

Required:

Master’s degree in Electrical Engineering or equivalent with 10+ years of relevant industry experience, or PhD with 8+ years

Deep, demonstrable expertise in the full UFS/Unipro/MPHY/RMMI protocol stack — knowledge broad enough to debug across layers and precise enough to pinpoint root cause efficiently; this is a hard requirement, not a nice-to-have

Fluent in SystemVerilog/Verilog RTL design and verification. Able to write, review, and rigorously debug RTL constructs as used in hardware emulation environments

Advanced English written and verbal fluency — essential for a globally integrated team whose communication runs through English at every level

Proven debugging skill and the discipline to stay methodical, patient, and precise under customer pressure

Emotionally intelligent; a natural collaborator who brings steadiness, genuine curiosity, and a real interest in the people across the table — customers and teammates alike

Strongly Preferred:

Hands-on experience with Cadence Palladium and/or Protium emulation platforms

Familiarity with scripting environments (Perl, TCL, C-shell)

Breadth of protocol exposure beyond UFS — SDRAM families, NAND Flash, or other complex communication protocols — enough to consult credibly across our wider MMP team

Experience navigating diverse customer behavioral styles across cultures and building trusted, long-term technical relationships

We’re doing work that matters. Help us solve what others can’t.