NXP

Sr. Principal Digital Designer

India · Work style not stated · Full time

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About the role

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EmployerNXP
LocationIndia
Work styleWork style not stated
Employment typeFull time
Employer posted28 Jul 2026

Role Summary

We are seeking a Sr. Principal Digital Designer to lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies).

The role involves driving digital micro-architecture, state machines, PCS functionality, safety mechanisms, and end‑to‑end digital design across the PHY.

Key Responsibilities

1. Architecture & Technical Leadership

Define and own digital subsystem micro‑architecture for Automotive Ethernet PHYs, including:

PCS pipelines and encoding/decoding logic
Scramblers/descramblers, CRC engines, alignment & framing
Packet processing, link monitoring, error handling
Interface logic (MII, RMII, RGMII, GMII, XGMII depending on product line)
Processor based SoC design

Show full description

Perform system‑level partitioning between digital, analog/mixed-signal, and firmware components.
Lead feasibility studies, power/performance trade-offs, and digital architecture exploration.

2. RTL Design & Implementation

Develop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic.
Drive digital front-end flows including:

Lint, CDC/RDC, reset architecture, synthesis guidance
Timing constraints and logic optimization

Work with DV to define coverage goals, corner cases, and feature verification plans.

3. System‑Level Ownership

Translate system requirements, IEEE 802.3 specifications, and architecture documents into robust digital designs.
Work with mixed-signal teams to define:

Control interfaces to analog front‑end blocks
Calibration engines, register programming flows, and digital‑analog interaction models

Contribute to bring‑up sequences, compliance testing, and system validation.

4. Automotive Quality & Functional Safety

Ensure compliance with Automotive Ethernet standards, ISO 26262, and AEC‑Q100 expectations.
Define and implement:

Safety mechanisms (BIST, LBIST/MBIST, error detection schemes)
Diagnostic monitors, timeout recovery logic, watchdogs, and fault reporting

Participate in FMEDA, DFA, and functional safety analysis.

5. Cross‑Functional Collaboration

Partner with:

Firmware/software teams for register maps, boot flows, diagnostics
PD teams to ensure implementation‑friendly architecture
Validation and compliance teams for pre‑ and post‑silicon debug

Mentor junior engineers and guide technical decision‑making across the digital team.

Required Qualifications

Masters in Electrical Engineering, Computer Engineering, or related discipline.
12+ years experience in digital design for PHY, SerDes, networking ASICs, or communication ICs.
Strong expertise in:

Verilog/SystemVerilog RTL design
High‑speed digital logic, state machines, control logic
IEEE 802.3 Ethernet PCS, link training, and system control flows
Synthesis, STA, CDC/RDC methodology

Proven track record across multiple production tape-outs.

Preferred Qualifications

Experience with Automotive Ethernet standards: 10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, 10GBASE‑T1.
Familiarity with PHY firmware-driven initialization and configuration flows.
Strong debugging skills with logic analyzers, protocol analyzers, and post-silicon validation.
Background in safety‑critical digital logic designs.

Soft Skills

Strong leadership, technical decision-making, and mentoring capabilities.
Ability to communicate complex architectural topics to multidisciplinary teams.
Excellent documentation and cross-functional collaboration skills.

More information about NXP in India...

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