Sr. Staff AI System Software Engineer

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Job Description:

The Role

As an AI Systems Software Engineer, you will work with system architecture, hardware engineering, compiler, and software engineering teams to design and evaluate systems that combine RISC-V CPUs, RISC-V AI accelerators, memory subsystems, and high-speed interconnects. You will help design software implementations that take advantage of accelerator hardware features and integrate cleanly with existing operating systems and machine-learning software stacks.

You will develop system software across the Linux stack including but not limited to device drivers, heterogeneous memory management, accelerator runtimes, and hardware abstraction layers. Your work will enable efficient communication and memory sharing between RISC-V host processors and AI accelerators

You will be a part of the team creating a complete, open, and programmable AI computing platform based on the RISC-V instruction set architecture that will empower the next generation of generative AI and edge computing applications.

Responsibilities

• Design and develop system software for RISC-V AI accelerator platforms, including Linux kernel components, device drivers, DMA engines, and memory-management subsystems.
• Develop and optimize device-side low-level runtime to maximize RISC-V AI accelerator throughput and latency hiding.
• Develop and integrate software for heterogeneous memory systems, including memory migration, page-fault handling, and Linux HMM-related mechanisms.
• Develop and optimize software for interfaces such as PCIe, CXL, IOMMU, ATS, PRI, PASID, and other host-to-accelerator communication mechanisms.
• Work with machine-learning framework teams to integrate accelerator runtimes with platforms such as PyTorch, TVM, MLIR, or related software stacks.
• Engage with system architecture, hardware engineering, firmware, compiler, and other software engineering teams to review and refine hardware and software features.
• Analyze and optimize system performance, including memory bandwidth, data-transfer overhead, address-translation latency, cache coherency, synchronization, and accelerator utilization.
• Develop benchmarks, profiling tools, tracing infrastructure, and performance regression tests for AI workloads.
• Debug complex issues across user space, the Linux kernel, firmware, FPGA prototypes, and accelerator hardware.

Requirements

• This position involves development of software for AI accelerators, heterogeneous memory systems, and interfaces such as PCIe, CXL, and IOMMU. Strong knowledge of computer architecture, virtual memory, and DMA is required.
• 8+ years of experience developing architecture-level code, operating-system components, or device drivers in C or C++ for multiprocessor and multithreaded systems such as Linux or BSD.
• Experience with device drivers, memory management, DMA, interrupts, synchronization, virtualization, or IOMMUs.
• Experience debugging complex multicore or heterogeneous systems.
• Experience debugging with tools such as GDB, JTAG, OpenOCD, perf, ftrace, or equivalent tools.
• Experience with Git, Makefiles, the GNU toolchain, and shell scripting.
• Experience working with hardware architecture and engineering teams.
• Strong understanding of computer architecture, including virtual memory, cache coherency, address translation, and interrupt handling.
• Strong communication, collaboration, and listening skills.
• B.Sc. or M.Sc. in Computer Science, Computer Engineering, Electrical Engineering, or a related discipline, or equivalent practical experience.

Preferred Qualifications

• Experience developing firmware and software for GPUs, NPUs, TPUs, or other AI accelerators.
• Experience with PCIe, CXL, ATS, PRI, PASID, cache-coherent interconnects, or accelerator memory systems.
• Familiarity with CUDA Unified Virtual Addressing, CUDA Unified Memory, AMD ROCm, HMM, OpenCL Shared Virtual Memory, or similar heterogeneous memory systems.
• Experience integrating custom hardware or accelerator runtimes with PyTorch, TVM, MLIR, or other machine-learning frameworks.
• Experience implementing or modifying Linux Heterogeneous Memory Management, mmu_notifier, mmu_interval_notifier, or related Linux memory-management components.
• Experience with RISC-V architecture, including paging, privilege levels, interrupts, exceptions, SBI, or platform firmware.
• Experience with performance analysis using hardware performance counters and system-level profiling tools.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Taiwan

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.