Staff Analog Design Engineer

What You Will Do

Design analog-mixed signal circuits using industry-standard tools such as Cadence and Synopsys

Develop schematic-level circuit designs and conduct system-level performance analysis

Build test benches to support simulation and verification, including Monte Carlo yield analysis across PVT corners

Guide layout engineers on circuit layout in deep sub-micron process nodes (7nm and below), including hands-on minor layout adjustments as needed

Partner with backend engineers to integrate design and layout, and provide circuit models to support backend verification

Support testboard design for silicon bring-up, bench debug, and characterization

Build scripts to support silicon bring-up and test feature validation

What You Will Bring

BS, MS, or PhD in Electrical Engineering with 5+ years of related professional experience in high-speed circuit design (e.g., phase interpolators, clocking, PLL design)

Experience with schematic capture, SPICE simulation, and Monte Carlo simulation

Experience with circuit layout, extraction, and back-annotated simulation

Experience with channel modeling using MATLAB or similar tools

Strong cross-functional communication and collaboration skills, with the ability to work effectively across distributed, cross-site teams

Strong analytical and problem-solving skills, with the ability to manage multiple priorities in a fast-paced environment

Preferred Qualifications

We'd be excited about candidates with deep expertise in any one of the following areas:

SerDes verification & characterization — building/maintaining analog verification infrastructure (testbenches, regressions, Monte Carlo campaigns), migrating blocks across process nodes, or reliability analysis (EM, IR drop, ESD/latch-up)

Clocking & CDR — ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon at 25 Gbps+ per lane, including bang-bang/baud-rate/DSP-assisted CDR architectures

TX/RX datapath — high-speed driver or receive front-end design (CTLE, VGA, samplers), DFE/FFE equalization, or PAM4/DSP-based receiver architectures

Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), familiarity with relevant specs (OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/7), or standards body participation

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.