System Level Test (SLT) Content Development and Debug Engineer

Key Responsibilities

• Develop test plans, test methods, execution, data analysis, builds automation and regression scripts, and creates automated verification flows for products including FPGA, transceiver, and multi-chip packages on bench or automatic test equipment.
• Understands IP subsystem validation requirements, including functional tests coverage needs within specifications, and corrective actions are put in place to catch any silicon failures.
• Performs debug to root cause product issues, from production rejects (RV) and/or customer reported failures (FACR) and execute workaround to patch the test holes to improve product quality.
• Works with various cross-functional teams to evaluate integrated system performance and to test and characterize device functionality at various operating conditions.
• Contributes to the product health indicators (PHI) definition and test hole reduction of defects per million (DPM) for quality monitoring.
• Creates platform validation documentation including risk assessments, test plans, user acceptance tests, and reports.

Qualifications:

Minimum Qualifications

• Bachelor’s / Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience defining and executing system-level, platform, silicon, or product validation plans and test methods.
• Experience developing automated test, regression, or verification scripts; analyzing data; and debugging failures to root cause.
• Experience working cross-functionally with hardware architecture and design, silicon validation, software, integration, process engineering, and manufacturing teams.
• Experience with bench or automatic test equipment validation and characterization of system performance, timing, power, thermal behavior, or hardware-software interaction.

Preferred Qualifications

• Experience in generating test contents and vectors to validate FPGA or multi-chip package products covering various IP subsystems such as core, configuration, transceiver, HPS, EMIF, LVDS, MIPI etc.
• Experience developing test automation and maintaining test frameworks, regression infrastructure, or enterprise-service integrations.
• Experience evaluating or deploying platform production test equipment and defining manufacturing test methodologies.
• Knowledge in Verilog / VHDL, Quartus Prime RTL generation including timing closure, and scripting languages such as TCL, Python etc.
• Strong system-level problem-solving, data-analysis, technical communication, and cross-functional collaboration skills.
• Candidates who are highly motivated, self-driven, initiative and resourceful would be suitable for this job scope.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.