Ciena
THW Client Co-op (January 2027 - Rochester, NY)
United States · Work style not stated · Full time
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About the role
Description from the employer’s posting. Check the employer’s page for the current version.
- EmployerCiena
- LocationUnited States
- Work styleWork style not stated
- Employment typeFull time
- Employer posted
As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.
The Opportunity: 4 month work term, starting January 2027
Join the ASIC IP team and contribute to the design and verification of client protocol mapping IP used in Ciena's WaveLogic coherent engine chipsets. This role provides hands-on exposure to digital ASIC development, verification methodologies, prototype development, automation, and optical networking technologies. The position offers opportunities to build technical experience while contributing to defined engineering deliverables.
Show full description
How you will make an impact:
- Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation.
- Collaborate with design and verification engineers on client subsystem and core development activities.
- Implement digital designs using SystemVerilog, Verilog, and VHDL.
- Verify digital designs using SystemVerilog and UVM methodologies.
- Develop and enhance prototype and development automation solutions.
- Apply communications standards knowledge, including IEEE 802.3, ITU, and OIF specifications, within development activities.
- Contribute to digital ASIC development projects through assigned engineering tasks.
The must haves:
- Education: Actively enrolled in a Bachelor’s degree program in Electrical Engineering or Computer Engineering,
- Previous experience with ASIC or FPGA development, as well as knowledge of and experience using System Verilog, Verilog, VHDL and Python
- Strong verbal and technical writing skills
- Self-motivated, and the ability to work independently as well as in a team environment
Nice to haves:
- Knowledge of OTN, Ethernet, and other Optical Networking standards
- Strong problem solving and debugging skills
- Experience working in a Linux environment
Pay Range:
The hourly pay range for this position is $27.00 - $37.50
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
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At a glance
- Employment typeFull time
- Employer posted
- Added to ROLIVA
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Skills in this posting
Skills ROLIVA found in the employer’s own description above. A mention is not a requirement.