DFT Engineer

As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy

Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support

• Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards

Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices

Test Pattern Development & Optimization

• Generate and optimize high-quality test and debug patterns for production
• Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
• Drive test coverage and quality metrics to meet stringent manufacturing requirements

Cross-Functional Collaboration & Methodology Innovation

• Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
• Participate in developing and maintaining cutting-edge DFT implementation flows
• Automate and improve methodologies using advanced scripting and tools

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field

4+ years of hands-on experience in DFT roles at semiconductor companies

Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG

Good understanding of logic design, verification, debug, and Static Timing Analysis (STA)

• Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation

Preferred Qualifications

• Master's degree in Electrical Engineering or related field

Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent)

Experience in chip bring-up and mass production activities

• Background in advanced process technologies (7nm and below)

Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements

Excellent communication skills with ability to work effectively in global team environments

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.