Astera Labs

IP Design Director

Bengaluru, Karnataka, India · Work style not stated

Apply on the employer’s site ↗See how well you match this job

You apply directly with the employer. ROLIVA does not submit applications from this page and is not the employer.

About the role

Description from the employer’s posting. Check the employer’s page for the current version.

  • EmployerAstera Labs
  • LocationBengaluru, Karnataka, India
  • Work styleWork style not stated
  • Employer posted

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description – IP DigitalDesign Manager

Position Overview

We are seeking an experienced and highly motivated Digital Design Manager to lead the micro-architecture, design, development, and delivery of IPs and Subsystems from for next-generation switch products. This role combines deep technical expertise with strong people leadership and program management skills.

Show full description

The successful candidate will be responsible for managing a team of IP digitaldesign engineers while driving the successful execution of complex IP development programs. The role requires close collaboration with Architecture, Verification, Physical Design, DFT, Firmware, Software, Product Engineering, and SoC Integration teams to ensure delivery of high-quality IPs that meet performance, power, area, quality, and schedule objectives.

This position offers the opportunity to influence product roadmaps, establish engineering best practices, and contribute to the development of industry-leading semiconductor solutions.

Key Roles & Responsibilities

Technology Background

  • Deep understanding of complex networking protocols such as PCIE, UALink, Ethernet is a must
  • Experience of working on latest generations of these protocols is highly desirable.
  • Expertise of standard front-end design flows / tools / HDLs for digital design

Technical Leadership

  • Lead the end-to-end development of digital Ips / Subsystems from architecture through silicon validation.
  • Partner with architects and product teams to define IP requirements, features, performance targets, and scalability needs.
  • Drive microarchitecture development and ensure alignment with overall SoC and product requirements.
  • Review and approve architecture specifications, design documents, RTL implementations, and verification plans.
  • Ensure IP designs achieve performance, power, area (PPA), reliability, and quality targets.
  • Lead technical reviews and provide guidance on complex design challenges.
  • Drive design trade-off decisions and risk mitigation strategies.
  • Lead the post-silicon support once silicon is back in the lab. Prior experience of post-silicon work is highly desirable.

IP Development & Delivery

  • Own the successful delivery of IP/Subsystem releases according to committed schedules and quality goals.
  • Ensure all IP deliverables, including RTL, verification collateral, documentation, synthesis constraints, and integration guides, are completed and released on time.
  • Drive IP reuse strategies to maximize engineering efficiency across multiple products and platforms.
  • Establish standards for IP packaging, version control, configuration management, and release processes.
  • Ensure compliance with internal design methodologies and industry best practices for all front-end flows such as Lint, CDC, Power Analysis, Timing Constraints.
  • Work with cross-functional teams to ensure that requirements, dependencies from all stakeholders are met and incorporated into the deliverables

Team Leadership & People Management

  • Build, lead, and mentor a high-performing IP design team.
  • Set clear goals and expectations for team members.
  • Conduct performance reviews, development planning, and regular coaching sessions.
  • Identify skill gaps and implement training and development initiatives.
  • Participate in workforce planning, recruiting, interviewing, hiring, and onboarding activities.
  • Foster an inclusive, collaborative, and innovation-driven culture.
  • Promote technical excellence and continuous learning within the organization.

Required Qualifications

Education

  • Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.
  • Master's degree preferred.

Experience

  • 15+ years of experience in semiconductor design and development.
  • 5+ years of experience managing engineering teams and complex IP development programs.
  • Proven track record of successfully delivering multiple IPs into production silicon.
  • Experience managing cross-functional engineering programs across geographically distributed teams.
  • Experience delivering IPs for AI, networking, datacenter, automotive, mobile, or high-performance computing products.
  • Experience leading global engineering teams.
  • Experience managing multiple concurrent IP development programs.
  • Familiarity with safety-critical and security-focused design methodologies.
  • Experience driving IP reuse strategies across multiple product generations.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Staying safe while you apply

  • Never pay to apply, interview or accept an offer. ROLIVA never asks you for payment to apply to a job.
  • Apply only through the official “Apply on the employer’s site” button, on the employer’s own site, and check that a recruiter’s email uses that employer’s own domain rather than a free email address.
  • Be cautious of an offer made with no real interview, or pressure to decide quickly or share financial details early.

Does something look wrong with this listing? Use “Report broken link” in the role details, or read ROLIVA’s full job-safety guidance ↗.

Preparing for this role with ROLIVA

  • Check the fit.

    Compare the requirements with the experience you have confirmed, including gaps.

  • Prepare honestly.

    Build interview stories and application drafts from your own evidence.

  • Keep track.

    Save the role and record your own application status and follow-ups.

Create a free workspace or log in.

At a glance

  • Employer posted
  • Added to ROLIVA
  • Last checked

Explore similar roles

Similar jobs

Astera Labs

DFT Engineer

Bengaluru, Karnataka, India

Work style not stated